In semiconductor fabrication, semiconductor chips are fabricated together on a single wafer. Fabrication of these chips generally involves forming several different structures on the wafer, including wiring lines, active devices and passive devices. These structures can be fabricated using conventional lithography, etching and deposition processes.
Scaling in semiconductor fabrication can be problematic, though, particularly beyond the 10 nm node. For example, in copper damascene processes, grain growth is constrained by narrow trenches into which copper is deposited. However, as pitch size is continually shrinking (e.g., coming closer together), it is becoming ever more difficult to pattern, e.g., cut, the metal lines or other structures in subsequent fabrication processes. For example, with the shrunken pitches, cutting of metal lines may damage neighboring metal lines, particularly since there is no self-aligned scheme available after self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP).